The present invention generally relates to integrated circuit devices, and particularly to structures for isolating adjacent devices without the use of shallow trench isolation (STI).
Due to the nature of epitaxial growth and certain structural features of integrated circuit devices, epitaxially grown regions may exhibit undesirably formed shapes that impact device performance and reliability. For example, the formation of epitaxially grown raised source/drain regions at the edge of STI regions of semiconductor devices may cause the raised source/drain regions to have faceted shapes at the STI region edges. The faceted shape of these raised source/drain regions may reduce the surface area of the raised source/drain regions. This reduced surface area in turn may undesirably increase the resistance between the raised source/drain regions and any formed contacts that are operable to provide device connectivity. Thus, since within integrated circuits a vast number of connections are needed, any degradation in connection resistance may compromise device operation within the integrated circuits and, therefore, lead to a reduction in device performance and yield.
FIG. 1 refer to a semiconductor structure 100 derived from a processes associated with growing epitaxial regions at the edges of STI regions formed on an SOI substrate, as is known in the art. In particular, FIG. 1 illustrates grown source/drain regions 130 and 170 for nFET and pFET devices 101 and 103, respectively. As depicted, the source/drain regions 130, 170 are grown at the edge of STI region 102, which includes divots 140, 180.
Source/drain regions 130 and 170 are formed after creating STI region 102. As depicted, the STI region 102 includes divots 140 and 180, which are a bi-product of the STI formation process. Since the STI region 102 and its corresponding divots 140, 180 are formed prior to growth of the source/drain regions 130, 170, during such epitaxial growth; faceting occurs at the respective interfaces 138, 141 between the grown source/drain regions 130, 170 and the STI region 102. Accordingly, based on the created facets 176, 132 that result from the formed divots 180, 140 associated with STI region 102, source/drain regions 130 and 170 include reduced contact surfaces S1 and S1′ for connecting to contacts 190b and 190c, respectively. The reduced surfaces may establish a poor electrical connection with the contacts 190b, 190c. Poor electrical connections cause increased contact resistance and, therefore, a potential device operation failure.
In contrast, source/drain regions 128 and 172, which are not located adjacent the STI region 102, are not effected by the STI region's 102 formed divots 180, 140 and, therefore, do not exhibit the faceting observed at source/drain regions 130 and 170. Therefore, contact surfaces S2 and S2′ for connecting to contacts 190a and 190d, respectfully, provide optimal electrical connectivity relative to contact surfaces S1 and S1′.
Source/drain regions which are bounded by STI regions are important to the layout of practical circuits. They isolate connections to unrelated transistors in a circuit, allowing flexibility in the placement and connectivity between transistors. One potential solution to the contact degradation requires the addition of an additional unused gate to allow the extension of adjacent source/drain regions make them similar to non-STI bounded ones. This results in the addition of one unused device space for every required device break, resulting in a significant loss in circuit density of upwards of 20%. Therefore, a process which allows for the isolation of adjacent transistors without incurring the reduced quality source/drain regions while reducing the loss of circuit density is desirable.